D-band CMOS transceiver chipset achieves 640 Gbps

A new D-band CMOS transceiver chipset has achieved the highest known transmission rate for a wireless device realised with integrated circuits (ICs), making it highly promising for the next generation of wireless systems.

To achieve faster speeds and handle increasing data traffic, wireless systems are operating in higher millimetre-wave frequency bands. Current high-band 5G systems offer speeds as high as 10 Gbps and operate in frequency bands between 24–47 GHz; the next generation of mobile communication systems is exploring even higher frequency bands.

Within this spectrum, the D band (covering frequencies from 110 to 170 GHz) is expected to play a crucial role in the development of the next generation of wireless systems. While high frequencies provide faster data speeds, they are susceptible to attenuation. Therefore, for the widespread adoption of next-generation wireless systems, cost-effective transmitters and receivers capable of maintaining signal strength are crucial.

Professor Kenichi Okada and his team at the Tokyo Institute of Technology, in collaboration with Japan’s National Institute of Information and Communications Technology, have now developed a novel transceiver chipset for the D-band. The chipset was fabricated using the popular 65 nm silicon complementary metal-oxide-semiconductor (CMOS) process, making it cost-effective for mass production. The result was a D-band CMOS transceiver chipset covering a 56 GHz signal-chain bandwidth, as revealed at the 2024 IEEE Symposium on VLSI Technology & Circuits.

The transceiver, with a chip size of 1.87 x 3.30 mm for the transmitter IC and 1.65 x 2.60 mm for the receiver IC, uses components designed to maintain signal speed and quality across a broad frequency spectrum. These include power amplifiers for elevating signals to suitable levels, low-noise amplifiers for boosting signal strength while minimising noise, frequency converters (mixers) for adjusting signals to the desired frequency range, distributed amplifiers for linearity, and frequency multipliers for quadrupling the frequency.

To assess the wireless transmission capabilities, the researchers mounted the chipset on a PCB and connected it to an external antenna with a gain of 25 dBi. The signal was converted from a transmission line format, typically used on PCBs, to a waveguide format, used for high-frequency signal transmission in wireless applications, with the conversion loss kept to 4 dB. The researchers successfully achieved high linearity for multi-level modulation schemes like 16 and 32QAM (QAM referring to quadrature amplitude modulation), solving a major roadblock for IC transceivers.

In testing with a modulated signal with a symbol rate of 40 Gbaud and 32QAM modulation at a distance of 36 cm, the system achieved a transmission speed of 200 Gbps with high modulation accuracy, with a bit error rate of less than 10^-3. Furthermore, using 16QAM modulation and a high-gain antenna (with a gain of 43 dBi), the researchers were able to achieve speeds of 120 Gbps over a distance of 15 m.

The chipset’s performance was further enhanced in a multiple-input multiple-output configuration with four transmitters and four receiver modules. Here, each antenna can handle its own data stream, enabling fast communication. Using 16QAM modulation, each channel reached a speed of 160 Gbps, resulting in a total speed of 640 Gbps — significantly faster than current 5G systems.

“The proposed chipset holds promise for the next generation of wireless systems to support automated cars, telemedicine and advanced virtual reality experiences,” Okada concluded.

Image caption: The fabricated D-band transmitter/receiver chipset. Image credit: The 2024 IEEE Symposium on VLSI Technology & Circuits.