60 GHz PLL CMOS receiver

IMEC has presented a 60 GHz front-end receive chain and phase-locked loop.

These building blocks, shown at the International Solid State Circuits Conference in the US, pave the way to second-generation 60 GHz radios by 2010 which will rely solely on plain CMOS, true one-chip solutions.

IMEC also demonstrated multi-gigabit-per-second wireless communication with its 60 GHz module that integrates IMEC antenna and antenna interfaces with its 45 nm multiple antenna RF front-end chip.

IMEC is developing single-chip 60 GHz radios using CMOS technology. The RF part optimally benefits from the speed advantages of chip technology. The RF part optimally benefits from the speed advantages of chip technology scaling.

45 nm digital CMOS also achieves the high-speed, low power consumption and low-area specifications for the digital part.

By developing beam-forming solutions with a phased antenna array apporach, IMEC overcomes the low signal-to-noise performance from which 60 GHz silicon-based radios typically suffer.

Believed to be a first major breakthrough, presented at ISSCC, is the realisation of a digitally controlled 57–66 GHz receiver RF front-end in 45 nm digital CMOS with a noise figure of 6 dB.

Its small area of 150 x 150 µm², its power consumption of 19 mA at 1.1 V supply and full-digital control make it suitable for phased-array systems.

IMEC has also developed a fully integrated 57–66 GHz phase-locked loop. The PLL, which outperforms all previous designs in terms of tuning range, is said to be the first to provide quadrature output phases at mm-wave frequencies, such that it can be readily used in a zero-IF architecture.

The circuit consumes 78 mW at 1.1 V.

Based on the results, the organisation says it can realise uncompressed high-definition video distribution with 16 antenna paths over 10 m with a power consumption of 1.6 W for the complete receiver.