National Semiconductor IF sampling receiver reference design

National Semiconductor has announced an IF sampling receiver reference design for multi-carrier, multi-standard wireless base stations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards.

The SP16160CH1RB reference design board facilitates evaluation of the IF receive signal path performance under a variety of input conditions. When combined with a low-noise, high-linearity RF front-end and sufficient IF filtering, the design enables high-sensitivity receivers that exceed multi-carrier GSM requirements in both normal and blocking conditions.

The sub-system delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally controlled variable gain amplifier set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA.

In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the board delivers sensitivity of -86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC’s high spurious-free dynamic range (SFDR).

The device operates from a single 5 V supply and includes the dual-channel ADC16DV160 16-bit, 160 megasamples per second pipeline ADC, dual-channel LMH6517 DVGA and LMK04031B clock jitter cleaner.

The overall performance of the reference design is enabled by the high dynamic performance of the ADC, the low noise and high linearity of the DVGA and ultra-low rms jitter of the clock jitter cleaner.

The ADC16DV160 delivers a signal-to-noise ratio of 76.3 dBFS and SFDR of 91.2 dBFS at 192 MHz input IF, while the LMH6517 provides a noise figure of 6 dB and OIP3 of 45 dBm, and the LMK04031B clock jitter cleaner offers near 150 fs of rms clock jitter.