Teledyne e2V development kit for mixed-signal subsystems

Teledyne e2v has expanded the scope of engineering support accompanying its EV12AQ60x analog-to-digital converter (ADC) series. The EV12AQ600-FMC-EVM development kit is a tool for those implementing mixed-signal subsystems.

Intended for prototyping work relating to avionics, military, space, telecommunications, industrial and high energy physics applications, this kit may be used for evaluating the operation of the company’s EV12AQ600 and EV12AQ605 12-bit quad-channel ADCs. It means that engineers can quickly construct functioning prototypes and check that the expected operational parameters can be achieved.

Each board features either an EV12AQ600 or an EV12AQ605 device, along with four single-ended signal inputs and an FMC connector for interfacing with an appropriate programmable logic device. In addition, a high-speed internal clock (supporting 6.4 GHz operation), a 12 V-rated power supply unit and an ESI-stream serial interface have also been incorporated, plus provision for the connection of an external clock and a temperature monitor.

The new development kit adds a further dimension to the existing portfolio of hardware based on the EV12AQ60x series. This also includes the previously introduced demo kit and the multi ADC synchronisation kit, both of which have built-in FPGAs. By the EV12AQ600-FMC-EVM allowing engineers to add their own relevant FPGA, consistent with what will be specified in their actual system, it is possible for them to begin creating the necessary code at the prototyping stage. This means that they don’t have to start again from scratch after the prototyping work has been completed. The kit is compatible with a wide variety of FPGA plug-in boards from different vendors. By utilising the ESI-stream interface, there is the possibility for multiple kits to be synchronised together to assist with the development of more complex arrangements, such as phased-array antennas.

The integrated cross-point switch can be used to sample the cores of each EV12AQ600 and EV12AQ605 ADC independently of one another or interleaved together. This results in a 1.6 GSps sampling rate when in 4-channel mode, a 3.2 GSps rate in 2-channel mode or a 6.4 GSps rate across a single channel. The bit rate and the input analog bandwidth can also be adjusted as required.